mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 99

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

The following figure provides the AC test load for TDO and the boundary-scan outputs of the device.
The following figure provides the JTAG clock input timing diagram.
The following figure provides the TRST timing diagram.
Freescale Semiconductor
For recommended operating conditions, see
Input hold times
Output valid times:
Output hold times
Notes:
1. The symbols used for timing specifications follow the pattern t
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of t
4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
and t
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
the high (H) state or setup time. Also, t
reaching the invalid state (X) relative to the t
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must
be added for trace lengths, vias, and connectors in the system.
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing
(first two letters of functional block)(reference)(state)(signal)(state)
External Clock
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
TRST
Parameter
JTAG
Output
Table 61. JTAG AC Timing Specifications (continued)
Boundary-scan data
Figure 52. AC Test Load for the JTAG Interface
Figure 53. JTAG Clock Input Timing Diagram
Table 3
VM
t
JTDXKH
JTKHKL
Figure 54. TRST Timing Diagram
VM
JTG
VM = Midpoint Voltage (OV
VM = Midpoint Voltage (OV
symbolizes JTAG timing (JT) with respect to the time data input signals (D)
Z
t
JTG
clock reference (K) going to the high (H) state. Note that in general, the clock
TDO
0
= 50 Ω
VM
t
TRST
Symbol
t
t
t
JTDXKH
JTKLDX
for outputs. For example, t
JTKLDV
(first two letters of functional block)(signal)(state)(reference)(state)
VM
1
DD
DD
R
TCLK
/2)
/2)
L
VM
Min
= 50 Ω
10
—
—
0
to the midpoint of the signal in question. The
t
JTGR
JTDVKH
OV
DD
JTG
Max
symbolizes JTAG device timing
15
10
t
—
—
JTGF
/2
clock reference (K) going to
Unit
ns
ns
ns
JTAG Controller
for inputs
Notes
—
3
3
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