mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 44

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

At recommended operating conditions with OV
Input Clocks
The following table provides the system clock (SYSCLK) AC timing specifications.
2.3.1
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter
specification given in below table considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output
jitter should meet the MPC8569E input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate
concerns; the MPC8569E is compatible with spread spectrum sources if the recommendations listed in the following table are
observed.
44
SYSCLK frequency
SYSCLK cycle time
SYSCLK duty cycle
SYSCLK slew rate
SYSCLK peak period jitter
SYSCLK jitter phase noise at –56 dBc
AC Input Swing Limits at 3.3 V OV
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their
2. Measured at the rising edge and/or the falling edge at OV
3. Slew rate as measured from ±0.3 ΔV
4. Phase noise is calculated as FFT of TIE jitter.
At recommended operating conditions with OV
Frequency modulation
Frequency spread
Notes:
1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.
respective maximum or minimum operating frequencies.
maximum specifications given in
Parameter/Condition
Spread Spectrum Sources
The processor’s minimum and maximum SYSCLK and core frequencies must not be
exceeded regardless of the type of clock source. Therefore, systems in which the processor
is operated at its maximum rated e500 core frequency should avoid violating the stated
limits by using down-spreading only.
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Parameter
Table 11. Spread Spectrum Clock Source Recommendations
DD
Table
Table 10. SYSCLK AC Timing Specifications
AC
t
SYSCLK/DDRCLK
DD
DD
10.
at the center of peak to peak voltage at clock input.
Symbol
f
t
= 3.3 V ± 165 mV
= 3.3 V ± 165 mV.
SYSCLK
SYSCLK
t
ΔV
KHK
—
—
—
AC
/
CAUTION
DD
Min
—
—
/2.
Min
7.5
1.9
66
40
—
—
1
Typ
Max
—
—
—
—
—
—
—
1.0
60
15.15
± 150
Max
133
500
60
—
4
Unit
kHz
%
Freescale Semiconductor
MHz
V/ns
Unit
KHz
ns
ps
%
V
Notes
1, 2
—
Notes
1, 2
1, 2
—
—
2
3
4