mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 79

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Common Mode Voltage, V
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (V
the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV.
In other words, V
The peak-to-peak differential voltage (V
2.9.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes.The SerDes reference clock inputs are SD_REF_CLK and SD_REF_CLK for PCI Express, Serial RapidIO, and
SGMII interface, respectively.
The following sections describe the SerDes reference clock requirements and provide application information.
2.9.2.1
SD_REF_CLK/SD_REF_CLK are designed to work with spread spectrum clock for PCI Express protocol only with the
spreading specification defined in
partners should use the same reference clock. For best results, a source without significant unintended modulation must be used.
The spread spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread spectrum
supported protocols. For example, if the spread spectrum clocking is desired on a SerDes reference clock for PCI Express and
the same reference clock is used for any other protocol such as SGMII/SRIO due to the SerDes lane usage mapping option,
spread spectrum clocking cannot be used at all.
2.9.2.2
The following figure shows a receiver reference diagram of the SerDes reference clocks.
Freescale Semiconductor
At recommended operating conditions. See
Frequency modulation
Frequency spread
Note:
1. Only down spreading is allowed.
SerDes Reference Clocks
SerDes Spread Spectrum Clock Source Recommendations
SerDes Reference Clock Receiver Characteristics
OD
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (V
Table 46. SerDes Spread Spectrum Clock Source Recommendations
cm
signal trace curve in a differential waveform. The voltage represented in the differential waveform
is not referenced to ground. See
The common mode voltage is equal to half of the sum of the voltages between each conductor of
a balanced interchange circuit and ground. In this example, for SerDes output,
V
complimentary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. It may be different between the
receiver input and driver output circuits within the same component. It is also referred to as the DC
offset on some occasions.
Parameter
cm_out
Table
= (V
Table
DIFFp-p
46. When using spread spectrum clocking for PCI Express, both ends of the link
SD_TX
3.
) is 1000 mV p-p.
+ V
SD_TX
) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
Figure 43
Min
30
+0
as an example for differential waveform.
Max
–0.5
33
High-Speed SerDes Interfaces (HSSI)
Unit
kHz
%
DIFFp
Notes
) is 500 mV.
—
1
OD
) has
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