mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 106

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Local Bus Controller
The following figure shows the AC timing diagram for PLL bypass mode.
The above figure applies to all three controllers that eLBC supports: GPCM, UPM, and FCM.
For input signals, the AC timing data is used directly for all three controllers.
For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed
to delay by t
106
(Except LUPWAIT/LFRB)
acs
(LUPWAIT/LFRB)
(address phase)
(0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is t
Output Signals
(Except LALE)
(data phase)
Input Signals
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Input Signal
LAD/LDP
LCLK[m]
LALE
LAD
Figure 59. Enhanced Local Bus Signals (PLL Bypass Mode)
t
LBKLOV
t
LBIVKH
acs
+ t
LBKHOV
t
LBIVKL
t
.
LBIXKH
t
LBONOT
t
LBKLOX
t
Freescale Semiconductor
LBKLOZ
t
LBIXKL