mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 102

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Local Bus Controller
2.15.2.2
For PLL enable mode, all timings are relative to the rising edge of LSYNC_IN.
The following table describes the timing specifications of the enhanced local bus interface at BV
for PLL enable mode.
102
For recommended operating conditions, see
Enhanced local bus cycle time
Enhanced local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup
Input hold
Output delay
(Except LALE)
Output hold
(Except LALE)
Enhanced local bus clock to output high
impedance for LAD/LDP
LALE output negation to LAD/LDP output
transition (LATCH hold time)
Notes:
1. All signals are measured from BV
2. Skew measured between different LCLK signals at BV
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
4. t
5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
Table 65. Enhanced Local Bus Timing Specifications (BV
delivered through the component pin is less than or equal to the leakage current specification.
by LBCR[AHD]. The unit is the eLBC controller clock cycle. The eLBC controller clock refers to the internal clock that runs the
local bus controller, not the external LCLK. LCLK cycle = eLBC controller clock cycle × LCRR[CLKDIV]. After power on reset,
LBCR[AHD] defaults to 0 and eLBC runs at maximum hold time.
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
LBONOT
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
Enhanced Local Bus AC Timing Specifications for PLL Enable Mode
Parameter
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
DD
/2 of the rising edge of LSYNC_IN to BV
Table 3
t
t
Symbol
LBKH/
LBKSKEW
t
t
t
t
t
t
LBKHOV
LBKHOX
LBKHOZ
LBONOT
LBIVKH
LBIXKH
t
LBK
t
LBK
1
DD
(LBCR[AHD] = 1)
/2.
(LBCR[AHD]=0)
½ – 0.475 ns
1 – 0.475 ns
Min
7.5
1.0
0.6
45
—
—
—
2
DD
= 3.3 V 2.5 V and 1.8 V) —PLL Enabled Mode
DD
/2 of the signal in question.
Max
680
3.8
3.8
12
55
—
—
—
—
DD
eLBC controller
clock cycle in
(= 1 platform
clock cycle
= 3.3 V, 2.5 V and 1.8 V
Freescale Semiconductor
Unit
ns)
ns
ps
ns
ns
ns
ns
ns
%
LBONOT
is determined
Notes
—
—
—
—
—
5
2
3
4