mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 40

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Overall DC Electrical Characteristics
2.1.1.2
The following table provides information on the characteristics of the output driver strengths. The values are preliminary
estimates.
2.1.2
The MPC8569E requires its power rails to be applied in a specific sequence to ensure proper device operation. These
requirements are as follows for power up:
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
From a system standpoint, if any of the I/O power supplies ramp prior to the V
supply may drive a logic one or zero during power up, and extra current may be drawn by the device.
2.1.3
This section describes the AC electrical specifications for the RESET timing requirements of the MPC8569E. The following
table describes the specifications for the RESET initialization timing.
40
Enhanced local bus interface utilities signals
DDR2 signal
DDR3 signal
DUART, EPIC, I
Note:
1. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at T
Required assertion time of HRESET
Minimum assertion time of TRESET simultaneous to HRESET assertion
MPC8569 reference manual for the DDR impedance programming procedure through the DDR control driver register 1
(DDRCDR_1).
1.
2.
V
GV
DD
DD
, AV
Power Sequencing
RESET Initialization
2
Output Driver Characteristics
C, JTAG, system control
Driver Type
While V
GV
described above.
DD
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
_n, BV
DD
. Nevertheless, GV
DD
DD
is ramping, current may be supplied from V
Parameter
, LV
Table 5. RESET Initialization Timing Specifications
DD
n, OV
DD
Table 4. Output Drive Capability
DD
from an external supply should follow the sequencing
, ScoreVDD, XV
Programmable Output Impedance (Ω)
35 (half strength mode)
40 (half strength mode)
18 (full strength mode)
20 (full strength mode)
NOTE
DD
45
45
45
45
DD
through the MPC8569E to
DD
Min
10
25
J
core supply, the I/Os associated with that I/O
= 105° C and at GV
Max
—
—
Supply Voltage
GV
GV
BV
BV
BV
OV
DD
DD
DD
DD
DD
DD
Freescale Semiconductor
DD
SYSCLK
= 3.3 V
= 2.5 V
= 1.8 V
= 1.8 V
= 1.5 V
= 3.3 V
Unit
(min). Refer to the
ns
Notes
Notes
1, 2
3
—
—
1
1