mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 90

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Serial RapidIO (SRIO)
(RD and RD). Each signal swings between A volts and B volts where A > B. Using these waveforms, the definitions are as
follows:
To illustrate these definitions using real values, consider the case of a CML (current mode logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 and 2.0 V. Using these values,
the peak-to-peak voltage swing of the signals TD and TD is 500 mV p-p. The differential output signal ranges between 500 and
–500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.
2.11.2
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such
as inter-symbol interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening
at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The
most common equalization techniques that can be used are:
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The transmitter output signals and the receiver input signals TD, TD, RD, and RD each have a peak-to-peak swing of
A – B volts
The differential output signal of the transmitter, V
The differential input signal of the receiver, V
The differential output signal of the transmitter and the differential input signal of the receiver each range from A – B
to –(A – B) volts
The peak value of the differential transmitter output signal and the differential receiver input signal is A – B volts
The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 × (A
– B) volts
Pre-emphasis on the transmitter
A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.
The use of active circuits in the receiver. This is often referred to as adaptive equalization.
A Volts
B Volts
Equalization
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Figure 47. Differential Peak-Peak Voltage of Transmitter or Receiver
TD or RD
TD or RD
Differential Peak-to-Peak = 2 × (A – B)
ID
, is defined as V
OD
, is defined as V
RD
– V
TD
RD
– V
TD
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