mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet
mpc8569e
Manufacturer Part Number
mpc8569e
Description
Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC8569E.pdf
(126 pages)
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Freescale Semiconductor
Data Sheet: Technical Data
MPC8569E PowerQUICC III
Integrated Processor
Hardware Specifications
• High-performance, 32-bit e500 core, scaling up to
• Integrated L1/L2 cache
• Two DDR2/DDR3 SDRAM memory controllers with full
• Integrated security engine (SEC) optimized to process all
© 2008–2011 Freescale Semiconductor, Inc.
1.33 GHz, that implements the Power Architecture®
technology
– 2799 MIPS at 1.33 GHz (estimated Dhrystone 2.1)
– 36-bit physical addressing
– Double-precision embedded floating point APU using
– Embedded vector and scalar single-precision
– Memory management unit (MMU)
– L1 cache—32-Kbyte data and 32-Kbyte instruction
– L2 cache—512-Kbyte (8-way set associative)
ECC support
– One 64-bit or two 32-bit data bus configuration
– Up to 400 MHz clock (800 MHz data rate)
– Supporting up to 16 Gbytes of main memory
– Using ECC, detects and corrects all single-bit errors and
– Invoke a level of system power management by asserting
– Both hardware and software options to support
– Initialization bypass feature that allow system designers
the algorithms associated with IPsec, IKE, SSL/TLS,
iSCSI, SRTP, IEEE Std 802.11i™, IEEE Std 802.16™
(WiMAX), IEEE 802.1ae™ (MACSec), 3GPP, A5/3 for
GSM and EDGE, and GEA3 for GPRS.
– XOR engine for parity checking in RAID storage
– Four crypto-channels, each supporting multi-command
64-bit operands
floating-point APUs using 32- or 64-bit operands
detects all double-bit errors and all errors within a nibble
MCKE SDRAM signal on-the-fly to put the memory
into a low-power sleep mode
battery-backed main memory
to prevent re-initialization of main memory during
system power on following abnormal shutdown
applications
descriptor chains
• QUICC Engine technology
• High-speed interfaces (multiplexed) supporting:
• On-chip network switch fabric
• 133 MHz, 16-bit, 3.3 V I/O, enhanced local bus (eLBC)
• Enhanced secured digital host controller (eSDHC) used for
• Integrated four-channel DMA controller
• Dual I
• Programmable interrupt controller (PIC)
• IEEE Std 1149.1™ JTAG test access port
• 1.0-V and 1.1-V core voltages with 3.3-V, 2.5-V, 1.8-V,
• 783-pin FC-PBGA package, 29 mm × 29 mm
– Cryptographic execution units for PKEU, DEU, AESU,
– Four 32-bit RISC cores
– Supports Ethernet, ATM, POS, and T1/E1 along with
– IEEE Std 1588™ v2 support
– SPI and Ethernet PHY management interface
– One full-/low-speed USB interface supporting USB 2.0
– General-purpose I/O signals
– Two 1× Serial RapidIO interfaces (with message unit) or
– ×4/×2/×1 PCI Express interface
– Two SGMII interfaces
with memory controller
SD/MMC card interface
receiver/transmitter (DUART) support
1.5-V and 1.0-V I/O
AFEU, MDEU, KEU, CRCU, RNG and SEU- SNOW
associated interworking
one 4x interface
– Four Gigabit Ethernet interfaces (up to two with
– Up to eight 10/100-Mbps Ethernet interfaces
– Up to 16 T1/E1 TDM links (512 × 64 channels)
– Multi-PHY UTOPIA/POS-PHY L2 interface
SGMII)
(16-bit)
2
C and dual universal asynchronous
Document Number: MPC8569EEC
MPC8569E
FC–PBGA–783
29 mm × 29 mm
Rev. 0, 06/2011