mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 67

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
At recommended operating conditions with XV
Output differential voltage
(XV
Output impedance (single-ended)
Notes:
1. This does l not align to DC-coupled SGMII.
2. |V
3. The |V
4. The |V
0 & 1) or XMITEQEF (for SerDes lanes 2 & 3) bit field of the MPC8569E SerDes control register:
• The MSB (bit 0) of the above bit field is set to zero (selecting the full V
• The LSB (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
variation, SerDes transmitter is terminated with 100-Ω differential load between SD_TX[n] and SD_TX[n].
DD-Typ
OD
| = |V
OD
OD
at 1.1 V)
| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes lanes
| value shown in the Typ column is based on the condition of XV
Parameter
SD_TXn
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
– V
Table 36. SGMII DC Transmitter Electrical Characteristics (continued)
SD_TXn
2, 3, 4
|. |V
OD
| is also referred as output differential peak voltage. V
Symbol
|V
DD
R
OD
O
= 1.0 V ± 3% and 1.1 V ± 3%.
|
352.0
323.1
293.6
264.7
234.4
205.6
176.0
Min
40
550.0
504.9
458.7
413.6
366.3
321.2
275.0
Typ
50
DD-DIFF-p-p
DD-Typ
= 1.0V and 1.1 V, no common mode offset
amplitude—power up default);
797.5
732.1
665.1
599.7
531.1
465.7
398.8
Max
TX-DIFFp-p
60
= 2 × |V
Unit
mV
Ω
Ethernet Interface
OD
|.
setting: 1.09×
setting: 1.33×
setting: 1.71×
Equalization
setting: 1.0×
Equalization
Equalization
setting: 1.2×
Equalization
Equalization
setting: 1.5×
Equalization
Equalization
setting: 2.0×
Notes
—
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