mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 105

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

The following table describes the timing specifications of the enhanced local bus interface at BV
with PLL disabled.
Freescale Semiconductor
For recommended operating conditions, see
Enhanced local bus cycle time
Enhanced local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup
(except LUPWAIT/LFRB)
Input hold
(except LUPWAIT/LFRB)
Input setup
(for LUPWAIT/LFRB)
Input hold
(for LUPWAIT/LFRB)
Output delay
(Except LALE)
Output hold
(Except LALE)
Enhanced local bus clock to output high
impedance for LAD/LDP
LALE output negation to LAD/LDP output
transition (LATCH hold time)
Notes:
1. All signals are measured from BV
2. Skew measured between different LCLK signals at BV
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
4. t
5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.
6. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
delivered through the component pin is less than or equal to the leakage current specification.
by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not
the external LCLK. LCLK cycle = eLBC controller clock cycle × LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults
to 0 and eLBC runs at maximum hold time.
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
LBONOT
Table 66. Enhanced Local Bus Timing Specifications (BV
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
Parameter
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
DD
/2 of rising/falling edge of LCLK to BV
Table 3
t
Symbol
t
LBKH
LBKSKEW
t
t
t
t
t
t
t
t
LBONOT
LBKLOV
LBKLOX
LBKLOZ
LBIVKH
LBIXKH
LBIVKL
LBIXKL
t
LBK
/t
DD
LBK
1
/2.
(LBCR[AHD] = 0)
(LBCR[AHD] = 1)
1/2 – 1 ns
1 – 1 ns
DD
–3.5
Min
6.5
6.5
12
45
—
—
—
1
1
= 3.3 V, 2.5 V, and 1.8 V)—PLL Bypassed
DD
/2 of the signal in question.
Max
Enhanced Local Bus Controller
150
1.5
55
—
—
—
—
—
—
—
2
DD
= 3.3, 2.5, and 1.8 V DC
LBONOT
controller
platform
cycle in
eLBC
cycle
clock
clock
Unit
(=1
ns)
ns
ps
ns
ns
ns
ns
ns
ns
ns
%
is determined
Notes
—
—
—
—
—
—
6
2
5
3
4
105