mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 84

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

PCI Express
2.9.2.5
The following figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
The DC and AC specification of SerDes data lanes are defined in each interface protocol section (SGMII, PCI Express, or Serial
Rapid IO) in this document based on the application usage
Note that external AC-coupling capacitor is required for the above three serial transmission protocols with the capacitor value
defined in the specification of each protocol section.
2.9.2.6
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
2.10
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8569E.
2.10.1
For more information, see
2.10.2
This section contains the DC specifications for the physical layer of PCI Express on this device.
84
•
•
•
Section 2.6.4, “SGMII Interface Electrical Characteristics”
Section 2.10, “PCI Express”
Section 2.11, “Serial RapidIO (SRIO)”
PCI Express
PCI Express DC Requirements for SD_REF_CLK and SD_REF_CLK
PCI Express DC Physical Layer Specifications
SerDes Transmitter and Receiver Reference Circuits
Clocking Dependencies
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Transmitter
Figure 45. SerDes Transmitter and Receiver Reference Circuits
Section 2.9.2.3, “DC Level Requirement for SerDes Reference Clocks.”
50 Ω
50 Ω
SD_TXn
SD_TXn
SD_RXn
SD_RXn
50 Ω
50 Ω
Receiver
Freescale Semiconductor