mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 49

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

The following figure shows the DDR2 and DDR3 SDRAM interface input timing diagram.
Freescale Semiconductor
At recommended operating conditions with GV
Tolerated Skew for MDQS—MDQ/MECC
800 MHz data rate
667 MHz data rate
533 MHz data rate
400 MHz data rate
Note:
1. t
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
3. Parameters tested in DDR2 mode are to 400, 533, 667, and 800 MHz data rates and in DDR3 mode to 667 and 800 MHz data
captured with MDQS[n]. This must be subtracted from the total timing budget.
determined by the following equation: t
absolute value of t
rates.
CISKEW
MDQS[n]
Table 19. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
MDQ[x]
MCK[n]
MCK[n]
Parameter
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
CISKEW
Figure 8. DDR2 and DDR3 SDRAM Interface Input Timing Diagram
.
t
MCK
t
DISKEW
DISKEW
DD
of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3
= ±(T ÷ 4 – abs(t
Symbol
t
DISKEW
D0
D1
t
CISKEW
DISKEW
–425
–510
–635
–885
Min
—
)) where T is the clock period and abs(t
t
DISKEW
DDR2 and DDR3 SDRAM Controller
Max
425
510
635
885
—
DISKEW
3
(continued)
.This can be
Unit
ps
CISKEW
Note
) is the
2
2
2
2
2
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