mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 96

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

I
The following figure provides the AC test load for the I
The following figure shows the AC timing diagram for the I
96
At recommended operating conditions with OV
Noise margin at the LOW level for each connected
device (including hysteresis)
Noise margin at the HIGH level for each connected
device (including hysteresis)
Capacitive load for each bus line
Notes:
1. The symbols used for timing specifications herein follow the pattern t
2. The requirements for I
3. As a transmitter, the MPC8659E provides a delay time of at least 300 ns for the SDA signal (referred to as the V
4. The maximum t
2
C
SDA
SCL
inputs and t
with respect to the time data input signals (D) reaching the valid state (V) relative to the t
high (H) state or setup time. Also, t
condition (S) went invalid (X) relative to the t
symbolizes I
to the t
I2C Frequency Divider Ratio for SCL.”
SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the MPC8569E acts as the I
load on SCL and SDA are balanced, the MPC8569E does not generate an unintended START or STOP condition. Therefore,
the 300 ns SDA output delay time is not a concern. If under some rare condition, the 300 ns SDA output delay time is required
for the MPC8569E as transmitter, application note AN2919, referred to in note 4 below, is recommended.
I2C
S
clock reference (K) going to the high (H) state or setup time.
(first two letters of functional block)(reference)(state)(signal)(state)
2
C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
I2OVKL
t
t
I2CL
I2SXKL
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Parameter
2
must be met only if the device does not stretch the LOW period (t
C frequency calculation must be followed. See Freescale application note AN2919, “Determining the
Output
Table 57. I
I2SXKL
t
I2DXKL,
Figure 50. I
DD
of 3.3 V ± 5%
symbolizes I
t
2
I2DVKH
t
I2OVKL
C AC Timing Specifications (continued)
I2C
Figure 49. I
2
t
C bus master while transmitting, it drives both SCL and SDA. As long as the
I2CH
Z
clock reference (K) going to the low (L) state or hold time. Also, t
0
= 50 Ω
2
C Bus AC Timing Diagram
2
t
C.
I2SXKL
2
C timing (I2) for the time that the data with respect to the START
Symbol
2
2
C bus.
C AC Test Load
V
V
Cb
NH
NL
Sr
for outputs. For example, t
1
t
I2SVKH
(first two letters of functional block)(signal)(state)(reference)(state)
0.1 × OV
0.2 × OV
R
L
= 50 Ω
Min
—
DD
DD
t
I2PVKH
t
I2KHKL
I2CL
OV
I2C
I2DVKH
DD
) of the SCL signal.
clock reference (K) going to the
/2
Max
400
—
—
symbolizes I
P
Freescale Semiconductor
S
Unit
pF
V
V
2
C timing (I2)
IHmin
I2PVKH
t
I2KHDX
Notes
of the
—
—
—
for