mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 72

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Ethernet Interface
2.6.5
The following table provides the QUICC Engine block IEEE 1588 AC timing specifications.
The following figure shows the data and command output AC timing diagram.
72
QE_1588_CLK clock period
QE_1588_CLK duty cycle
QE_1588_CLK peak-to-peak jitter
Rise time QE_1588_CLK (20%–80%)
Fall time QE_1588_CLK (80%–20%)
QE_1588_CLK_OUT clock period
QE_1588_CLK_OUT duty cycle
QE_1588_PPS_OUT
QE_1588_TRIG_IN pulse width
QE_PTP_SOF_TX_IN pulse width
QE_PTP_SOF_RX_IN pulse width
Notes:
1. T
2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the QUICC Engine Block
3. The maximum value of t
4. The minimum value of t
5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
QUICC Engine Block with Protocol Interworking Reference Manual, for a description of TMR_CTRL registers.
with Protocol Interworking Reference Manual, for a description of TMR_CTRL registers.
example, for 10/100/1000 Mbps modes, the maximum value of t
t
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
TX/RXCLK
RX_CLK
is the max clock period of the QUICC Engine block’s receiving clock selected by TMR_CTRL[CKSEL]. See the
are 800, 80, and 16 ns, respectively.
QE_1588_CLK_OUT
QE_1588_PPS_OUT
1
QUICC Engine Block IEEE 1588 AC Specifications
QUICC Engine block IEEE 1588 Output AC timing: The output delay is counted starting at the rising
edge if t
Parameter
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Table 40. QUICC Engine Block IEEE 1588 AC Timing Specifications
T11588CLKOUT
TX/RXCLK
T1588CLK
Figure 31. QUICC Engine Block IEEE 1588 Output AC Timing
is defined by the recovered clock. For example, for 10/100/1000 Mbps modes, the value of
is not only defined by the value of t
is non-inverting. Otherwise, it is counted starting at the falling edge.
t
t
t
t
t
T1588CLKOTH
t
T1588CLKOUT
T1588CLKOUT
t
t
t
t
T1588CLKINR
T1588CLKINJ
T1588CLKINF
T1588TRIGH
T1588TRIGH
T1588TRIGH
T1588CLKH
t
t
Symbol
T1588CLK
T1588CLK
t
T1588OV
t
T1588CLKOUT
t
T1588OV
/
/
t
T1588CLKOUTH
2 × t
T1588CLK
2 × t
T
T
TX_CLK
RX_CLK
T1588CLK_
RX_CLK
T1588CLK
Min
MAX
3.8
1.0
1.0
0.5
40
30
—
are 2800, 280, and 56 ns, respectively.
× 2
× 2
, but also defined by the recovered clock. For
Typ
50
50
—
—
—
—
—
—
—
—
—
T
RX_CLK
Max
250
2.0
2.0
4.0
60
70
—
—
—
—
Freescale Semiconductor
× 7
Unit
ns
ps
ns
ns
ns
ns
ns
ns
ns
%
%
Notes
1, 3
—
—
—
5
5
5
5
2
4
4