upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 497

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Clock
monitor
Power-
on-clear
circuit
(POC)
Low-
voltage
detector
(LVI)
Option
byte
Function
CLM: Clock
monitor mode
register
Power-on-clear
circuit functions
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detection
register
LVIS: Low-
voltage detection
level selection
register
When used as
reset
Cautions for low-
voltage detector
0084H/1084H
Details of
Function
Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or
the internal reset signal.
If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit
1 (CLMRF) of the reset control flag register (RESF) is set to 1.
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
The supply voltage is V
subsystem clock is used, but be sure to use the standard products and (A) grade
products in a voltage range of 2.2 to 5.5 V because the detection voltage (V
the POC circuit is 2.1 V ±0.1 V.
The supply voltage is V
used, but be sure to use the (A1) grade products in a voltage range of 2.25 to 5.5
V because the detection voltage (V
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Be sure to clear bits 4 to 7 to 0.
Clear all port pins after the supply voltage (V
voltage (V
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
If supply voltage (V
internal reset signal is not generated.
In a system where the supply voltage (V
vicinity of the LVI detection voltage (V
on how the low-voltage detector is used.
(1) When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the
microcontroller can be arbitrarily set by taking action (a) below.
(2) When used as interrupt
Interrupt requests may be frequently generated. Take action (b) below.
Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not
equipped with the on-chip debug function (
78F0124H). Also set 00H to 1084H because 0084H and 1084H are switched at
boot swapping.
To use the on-chip debug function with a product equipped with the on-chip
debug function (
the same as that of 0084H to 1084H because 0084H and 1084H are switched at
boot swapping.
APPENDIX D LIST OF CAUTIONS
LVI
) after POC release in the (A1) grade products.
User’s Manual U16962EJ3V0UD
µ
PD78F0124HD), set 02H or 03H to 0084H. Set a value that is
DD
) ≥ detection voltage (V
DD
DD
= 2.0 to 5.5 V when the internal oscillation clock or
= 2.0 to 5.5 V when the internal oscillation clock is
POC
Cautions
LVI
) of the POC circuit is 2.0 to 2.25 V.
POC
), the operation is as follows depending
DD
DD
) fluctuates for a certain period in the
) fluctuates for a certain period in the
), the system may be repeatedly reset
µ
PD78F0122H, 78F0123H, and
DD
LVI
) exceeds the preset detection
) when LVIMD is set to 1, an
POC
) of
p. 362
p. 362
p. 368
p. 368
p. 368
p. 370
p. 373
p. 374
p. 374
p. 375
p. 375
p. 379
p. 382
p. 382
Page
(21/23)
497