upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 490

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

490
Serial
interface
UART0
Function
UART mode
TXS0: Transmit
shift register 0
ASIM0:
Asynchronous
serial interface
operation mode
register 0
ASIS0:
Asynchronous
serial interface
reception error
status register 0
BRGC0: Baud
rate generator
control register
0
Details of
Function
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may
not be initialized.
Set transmit data to TXS0 at least two base clocks after setting POWER0 = 1 and
one base clock after setting TXE0 = 1.
Do not write the next transmit data to TXS0 before the transmission completion
interrupt signal (INTST0) is generated.
At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear
TXE0 to 0, and then clear POWER0 to 0.
At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation,
clear RXE0 to 0, and then clear POWER0 to 0.
Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0
pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input,
reception is started.
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may
not be initialized.
Set transmit data to TXS0 at least two base clocks after setting POWER0 = 1 and
one base clock after setting TXE0 = 1.
Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0
bits.
Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always
performed with “number of stop bits = 1”, and therefore, is not affected by the set
value of the SL0 bit.
Be sure to set bit 0 to 1.
The operation of the PE0 bit differs depending on the set values of the PS01 and
PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0).
Only the first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer
register 0 (RXB0) but discarded.
If data is read from ASIS0, a wait cycle is generated. Do not read data from
ASIS0 when the CPU is operating on the subsystem clock and the high-speed
system clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the base clock is the internal oscillation clock, the operation of serial interface
UART0 is not guaranteed.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16962EJ3V0UD
Cautions
XCLK0
XCLK0
) set by BRGC0. To
) set by BRGC0. To
p. 247
p. 247,
250
p. 250
p. 252
p. 252
p. 252
p. 252
p. 252
p. 252
p. 252
p. 252
p. 253
p. 253
p. 253
p. 253
p. 255
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