upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 480

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

480
16-bit
timer/
event
counter
00
(TM00)
Function
CR000: 16-bit
timer
capture/compare
register 000
CR010: 16-bit
timer
capture/compare
register 010
TMC00: 16-bit
timer mode
control register
00
TMC00: 16-bit
timer mode
control register
00
Details of
Function
Set a value other than 0000H in CR000 in the mode in which clear & start occurs
on a match of TM00 and CR000.
If CR000 is set to 0000H in the free-running mode and in the clear mode using
the valid edge of the TI000 pin, an interrupt request (INTTM000) is generated
when the value of CR000 changes from 0000H to 0001H following TM00
overflow (FFFFH). Moreover, INTTM000 is generated after a match of TM00
and CR000 is detected, a valid edge of the TI010 pin is detected, and the timer
is cleared by a one-shot trigger.
When P01 is used as the valid edge input of the TI010 pin, it cannot be used as
the timer output (TO00). Moreover, when P01 is used as TO00, it cannot be used
as the valid edge input of the TI010 pin.
When CR000 is used as a capture register, read data is undefined if the register
read time and capture trigger input conflict (the capture data itself is the correct
value). If timer count stop and capture trigger input conflict, the captured data is
undefined.
Do not rewrite CR000 during TM00 operation.
If CR010 is cleared to 0000H, an interrupt request (INTTM010) is generated when
the value of CR010 changes from 0000H to 0001H following TM00 overflow
(FFFFH). Moreover, INTTM010 is generated after a match of TM00 and CR010 is
detected, a valid edge of the TI000 pin is detected, and the timer is cleared by a
one-shot trigger.
When CR010 is used as a capture register, read data is undefined if the register
read time and capture trigger input conflict (the capture data itself is the correct
value). If count stop input and capture trigger input conflict, the captured data is
undefined.
CR010 can be rewritten during TM00 operation. For details, see Caution 2 in
Figure 6-15.
16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and
TMC003 are set to values other than 0, 0 (operation stop mode), respectively.
Clear TMC002 and TMC003 to 0, 0 to stop the operation.
Timer operation must be stopped before writing to bits other than the OVF00 flag. p. 128
Set the valid edge of the TI000/P00 pin using prescaler mode register 00
(PRM00).
If any of the following modes: the mode in which clear & start occurs on match
between TM00 and CR000, the mode in which clear & start occurs at the valid
edge of the TI000 pin or free-running mode, is selected, when the set value of
CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00
flag is set to 1.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16962EJ3V0UD
Cautions
p. 125
p. 125
p. 125
p. 125
pp. 125,
133,
138,
150
p. 126
p. 126
p. 126
p. 127
p. 128
p. 128
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