upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 334

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16.4.3 Multiple interrupt servicing
(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during
interrupt servicing to enable interrupt acknowledgment.
interrupt priority control. Two types of priority control are available: default priority control and programmable priority
control. Programmable priority control is used for multiple interrupt servicing.
currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority
lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged
for multiple interrupt servicing.
a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is
acknowledged following execution of at least one main processing instruction execution.
shows multiple interrupt servicing examples.
334
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt
Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have
Table 16-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 16-10
Table 16-5. Relationship Between Interrupt Request Enabled for Multiple Interrupt Servicing
Interrupt Being Serviced
Maskable interrupt
Software interrupt
Remarks 1.
Multiple Interrupt Request
During Interrupt Servicing
2. ×: Multiple interrupt servicing disabled
3. ISP and IE are flags contained in the PSW.
4. PR is a flag contained in PR0L, PR0H, and PR1L.
ISP = 0: An interrupt with higher priority is being serviced.
ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower
IE = 0:
IE = 1:
PR = 0: Higher priority level
PR = 1: Lower priority level
: Multiple interrupt servicing enabled
ISP = 0
ISP = 1
priority is being serviced.
Interrupt request acknowledgment is disabled.
Interrupt request acknowledgment is enabled.
CHAPTER 16 INTERRUPT FUNCTIONS
User’s Manual U16962EJ3V0UD
IE = 1
PR = 0
Maskable Interrupt Request
IE = 0
×
×
×
IE = 1
×
PR = 1
IE = 0
×
×
×
Software
Interrupt
Request