upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 276

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

276
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0,
Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0,
3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If
4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
5. Fix the PS61 and PS60 bits to 0 when UART6 is used in the LIN communication operation.
6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the
7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
ISRM6
RXE6
PS61
CL6
and then clear POWER6 to 0.
and then clear POWER6 to 0.
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
SL6
0
1
0
0
1
1
0
1
0
1
0
1
Disables reception (synchronously resets the reception circuit).
Enables reception
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
PS60
0
1
0
1
Enables/disables occurrence of reception completion interrupt in case of error
CHAPTER 14 SERIAL INTERFACE UART6
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
User’s Manual U16962EJ3V0UD
Transmission operation
Specifies character length of transmit/receive data
Specifies number of stop bits of transmit data
Enables/disables reception
Reception without parity
Reception as 0 parity
Judges as odd parity.
Judges as even parity.
Reception operation
Note