upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 487

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Watchdog
timer
A/D
converter
Function
WDTM:
Watchdog timer
mode register
WDTE:
Watchdog timer
enable register
When “internal
oscillator cannot
be stopped” is
selected by
option byte
When “internal
oscillator can be
stopped by
software” is
selected by
option byte
ADM: A/D
converter mode
register
ADS: Analog
input channel
specification
register
ADCR: A/D
conversion
result register
PFM: Power-fail
comparison
mode register
Details of
Function
WDTM cannot be set by a 1-bit memory manipulation instruction.
If “internal oscillator can be stopped by software” is selected by the option byte
and the watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer
does not resume operation even if WDCS4 is cleared to 0. In addition, the
internal reset signal is not generated.
If a value other than ACH is written to WDTE, an internal reset signal is
generated. If the source clock to the watchdog timer is stopped, however, an
internal reset signal is generated when the source clock to the watchdog timer
resumes operation.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated. If the source clock to the watchdog timer is stopped,
however, an internal reset signal is generated when the source clock to the
watchdog timer resumes operation.
The value read from WDTE is 9AH (this differs from the written value (ACH)).
In this mode, operation of the watchdog timer absolutely cannot be stopped even
during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the
internal oscillation clock can be selected as the count source, so clear the
watchdog timer using the interrupt request of TMH1 before the watchdog timer
overflows after STOP instruction execution. If this processing is not performed, an
internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
In this mode, watchdog timer operation is stopped during HALT/STOP instruction
execution. After HALT/STOP mode is released, counting is started again using
the operation clock of the watchdog timer set before HALT/STOP instruction
execution by WDTM. At this time, the counter is not cleared to 0 but holds its
value.
A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other
than the identical data.
For the sampling time of the A/D converter and the A/D conversion start delay
time, see (11) in 12.6 Cautions for A/D Converter.
If data is written to ADM, a wait cycle is generated. Do not write data to ADM
when the CPU is operating on the subsystem clock and the high-speed system
clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
Be sure to clear bits 3 to 7 of ADS to 0.
If data is written to ADS, a wait cycle is generated. Do not write data to ADS
when the CPU is operating on the subsystem clock and the high-speed system
clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read
the conversion result following conversion completion before writing to ADM and
ADS. Using timing other than the above may cause an incorrect conversion result
to be read.
If data is read from ADCR, a wait cycle is generated. Do not read data from
ADCR when the CPU is operating on the subsystem clock and the high-speed
system clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
If data is written to PFM, a wait cycle is generated. Do not write data to PFM when
the CPU is operating on the subsystem clock and the high-speed system clock is
stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16962EJ3V0UD
Cautions
p. 215
p. 215
p. 215
p. 215
p. 215
p. 217
p. 218
p. 230
p. 230
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p. 231
p. 231
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