upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 420

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

420
16-bit
operation
Multiply/
divide
Increment/
decrement
Rotate
BCD
adjustment
Bit
manipulate
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
ADDW
SUBW
CMPW
MULU
DIVUW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
ROR4
ROL4
ADJBA
ADJBS
MOV1
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
AX, #word
AX, #word
AX, #word
X
C
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
[HL]
[HL]
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Operands
CHAPTER 26 INSTRUCTION SET
User’s Manual U16962EJ3V0UD
Bytes
3
3
3
2
2
1
2
1
2
1
1
1
1
1
1
2
2
2
2
3
3
2
3
2
3
3
2
3
2
Note 1
16
25
10
10
6
6
6
2
4
2
4
4
4
2
2
2
2
4
4
6
−
4
−
6
6
−
4
−
6
Clocks
Note 2
12
12
−
−
−
−
−
−
6
−
6
−
−
−
−
−
−
−
−
7
7
−
7
7
8
8
−
8
8
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
AX ← A × X
AX (Quotient), C (Remainder) ← AX ÷ C
r ← r + 1
(saddr) ← (saddr) + 1
r ← r − 1
(saddr) ← (saddr) − 1
rp ← rp + 1
rp ← rp − 1
(CY, A
(CY, A
(CY ← A
(CY ← A
A
(HL)
A
(HL)
Decimal Adjust Accumulator after Addition
Decimal Adjust Accumulator after Subtract
CY ← (saddr.bit)
CY ← sfr.bit
CY ← A.bit
CY ← PSW.bit
CY ← (HL).bit
(saddr.bit) ← CY
sfr.bit ← CY
A.bit ← CY
PSW.bit ← CY
(HL).bit ← CY
3 − 0
3 − 0
3 − 0
7 − 4
← (HL)
← (HL)
7
0
← A
← A
← (HL)
← (HL)
0
7
, A
, A
0
7
7
0
3 − 0
7 − 4
CPU
, A
, A
← CY, A
← CY, A
7 − 4
3 − 0
, (HL)
, (HL)
m − 1
m + 1
) selected by the processor clock
Operation
← A
← A
3 − 0
7 − 4
m − 1
m + 1
m
m
← A
← A
) × 1 time
) × 1 time
← A
← A
3 − 0
3 − 0
m
m
) × 1 time
) × 1 time
,
,
Z AC CY
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×