upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 383

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

23.2 Format of Option Byte
Address: 0080H/1080H
Address: 0081H/1081H, 0082H/1082H, 0083H/1083H
Address: 0084H/1084H
The format of the option byte is shown below.
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
Cautions 1. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
Note Be sure to set 00H to 0081H, 0082H, and 0083H, as these addresses are reserved areas. Also set 00H to
Notes 1.
Remark For the on-chip debug security ID, see CHAPTER 25 ON-CHIP DEBUG FUNCTION (
boot swap operation.
1081H, 1082H, and 1083H because 0081H, 0082H, and 0083H are switched with 1081H, 1082H, and
1083H when the boot swap operation is used.
2.
ONLY).
2. Be sure to clear bit 1 to 7 to 0.
Be sure to set 00H (on-chip debug operation disabled) to 0084H for products not equipped with the on-
chip debug function (
0084H and 1084H are switched at boot swapping.
To use the on-chip debug function with a product equipped with the on-chip debug function
(
because 0084H and 1084H are switched at boot swapping.
LSROSC
OCDEN1
µ
PD78F0124HD), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (RSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal oscillation clock, the count clock is supplied to
8-bit timer H1 even in the HALT/STOP mode.
7
0
0
1
7
0
7
0
0
0
1
1
Note
Notes1, 2
Can be stopped by software (stopped when 1 is written to bit 0 (RSTOP) of RCM register)
Cannot be stopped (not stopped even if 1 is written to RSTOP bit)
OCDEN0
6
0
6
0
6
0
0
1
0
1
µ
PD78F0122H, 78F0123H, and 78F0124H). Also set 00H to 1084H because
Operation disabled
Setting prohibited
Operation enabled. Does not erase data of the flash memory in case authentication
of the on-chip debug security ID fails.
Operation enabled. Erases data of the flash memory in case authentication of the
on-chip debug security ID fails.
Figure 23-1. Format of Option Byte
CHAPTER 23 OPTION BYTE
5
0
5
0
5
0
User’s Manual U16962EJ3V0UD
Note
4
0
4
0
4
0
Internal oscillator operation
On-chip debug operation control
3
0
3
0
3
0
2
0
2
0
2
0
OCDEN1
1
0
1
0
1
µ
PD78F0124HD
LSROSC
OCDEN0
0
0
0
0
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