upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 327

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
Cautions 3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, and MK1L can be set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H
are combined to form 16-bit register MK0, they can be set by a 16-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Caution Be sure to set bit 7 of MK1L to 1.
Address: FFE4H
Symbol
MK0L
Address: FFE5H
Symbol
MK0H
Address: FFE6H
Symbol
MK1L
TMMK010
SREMK6
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
In this case, even if the request flag of another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared
to 0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory
manipulation instruction in C language.
Figure 16-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L)
XXMKX
<7>
<7>
7
1
0
1
mov
and
mov
After reset: FFH
After reset: FFH
After reset: FFH
a, #0FEH
a, IF0L
IF0L, a
Interrupt servicing enabled
Interrupt servicing disabled
TMMK000
PMK5
PMK6
<6>
<6>
<6>
CHAPTER 16 INTERRUPT FUNCTIONS
R/W
R/W
R/W
TMMK50
WTMK
PMK4
<5>
<5>
<5>
User’s Manual U16962EJ3V0UD
TMMKH0
KRMK
PMK3
<4>
<4>
<4>
Interrupt servicing control
TMMKH1
TMMK51
PMK2
<3>
<3>
<3>
DUALMK0
WTIMK
PMK1
<2>
<2>
<2>
SRMK0
STMK6
PMK0
<1>
<1>
<1>
SRMK6
LVIMK
ADMK
<0>
<0>
<0>
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