upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 309

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

<R>
(2) Serial clock selection register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
CSIC10
Symbol
This register specifies the timing of the data transmission/reception and sets the serial clock.
CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Note Set the serial clock to satisfy the following conditions.
• V
• V
• V
• V
DD
DD
DD
DD
CKS102
CKP10
= 4.0 to 5.5 V: Serial clock ≤ 5 MHz
= 3.3 to 4.0 V: Serial clock ≤ 4.19 MHz
= 2.7 to 3.3 V: Serial clock ≤ 2.5 MHz
= 2.5 to 2.7 V: Serial clock ≤ 1.25 MHz (standard products, (A) grade products only)
7
0
0
0
1
1
0
0
0
0
1
1
1
1
Figure 15-3. Format of Serial Clock Selection Register 10 (CSIC10)
CKS101
DAP10
6
0
0
1
0
1
0
0
1
1
0
0
1
1
CHAPTER 15 SERIAL INTERFACE CSI10
CKS100
SI10 input timing
SI10 input timing
SI10 input timing
SI10 input timing
5
0
0
1
0
1
0
1
0
1
User’s Manual U16962EJ3V0UD
Specification of data transmission/reception timing
SCK10
SCK10
SCK10
SCK10
f
f
f
f
f
f
f
External clock input to SCK10
SO10
SO10
X
X
X
X
X
X
X
SO10
SO10
/2 (5 MHz)
/2
/2
/2
/2
/2
/2
CKP10
2
3
4
5
6
7
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(312.5 kHz)
(156.25 kHz)
(78.13 kHz)
4
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSI10 serial clock selection
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DAP10
3
CKS102
2
Note
CKS101
1
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
CKS100
Mode
Type
0
1
2
3
4
309