upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 331

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16.4 Interrupt Servicing Operations
16.4.1 Maskable interrupt request acknowledgment
(MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if
interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is
not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0).
16-4 below.
specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same
priority level, the request with the highest default priority is acknowledged first.
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is loaded into the
PC and branched.
A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask
The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table
For the interrupt request acknowledgment timing, refer to Figures 16-8 and 16-9.
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/f
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 16-7 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
Restoring from an interrupt is possible by using the RETI instruction.
Table 16-4. Time from Generation of Maskable Interrupt Request Until Servicing
When ××PR = 0
When ××PR = 1
CPU
(f
CPU
: CPU clock)
CHAPTER 16 INTERRUPT FUNCTIONS
User’s Manual U16962EJ3V0UD
7 clocks
8 clocks
Minimum Time
32 clocks
33 clocks
Maximum Time
Note
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