upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 488

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

488
A/D
converter
Function
PFT: Power-fail
comparison
threshold
register
A/D conversion
operation
Power-fail
detection
function
Operating
current in
standby mode
ANI0 to ANI7
input range
Conflict
operation
Noise
countermeasures
ANI0/P20 to
ANI7/P27
Details of
Function
If data is written to PFT, a wait cycle is generated. Do not write data to PFT when
the CPU is operating on the subsystem clock and the high-speed system clock is
stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
Make sure the period of <1> to <3> is 14
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, do not use the first conversion result after <3> in
this case.
The period from <4> to <7> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set
using FR2 to FR0.
Make sure the period of <3> to <6> is 14
It is no problem if order of <3>, <4>, and <5> is changed.
<3> must not be omitted if the power-fail function is used.
The period from <7> to <11> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <9> to <11> is the conversion time set
using FR2 to FR0.
The A/D converter stops operating in the standby mode. At this time, the
operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of
the A/D converter mode register (ADM) to 0 (see Figure 12-2).
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AV
or higher and AV
input to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
Conflict between A/D conversion result register (ADCR) write and ADCR read by
instruction upon the end of conversion
ADCR read has priority. After the read operation, the new conversion result is
written to ADCR.
Conflict between ADCR write and A/D converter mode register (ADM) write or
analog input channel specification register (ADS) write upon the end of
conversion
ADM or ADS write has priority. ADCR write is not performed, nor is the
conversion end interrupt signal (INTAD) generated.
To maintain the 10-bit resolution, attention must be paid to noise input to the
AV
Because the effect increases in proportion to the output impedance of the analog
input source, it is recommended that a capacitor be connected externally, as
shown in Figure 12-19, to reduce noise.
The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to
P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do
not access port 2 while conversion is in progress; otherwise the conversion
resolution may be degraded.
If a digital pulse is applied to the pins adjacent to the pins currently used for A/D
conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin
undergoing A/D conversion.
REF
pin and pins ANI0 to ANI7.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16962EJ3V0UD
SS
or lower (even in the range of absolute maximum ratings) is
Cautions
µ
µ
s or more.
s or more.
REF
p. 233
p. 239
p. 239
p. 239
p. 239
p. 239
p. 239
p. 239
p. 239
p. 242
p. 242
p. 242
p. 242
p. 242
p. 243
p. 243
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