MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 93

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

ORx
PSDMR
29–30 EHTR
0–16 AM
Bits
Bits
2–4
Addr
19
23
0
1
Bit
Bit
Bit
Bit
BCTLD
BI
PBI
RFEN
OP
RFRC
PBI
AM
16
16
0
0
(OR1) 0x1010C
Name
Name
(OR0) 0x10104
Option Register—UPM Mode
60x SDRAM Protocol-Specific Mode Register
RFEN
17
17
1
1
PRETOACT
—
Address Mask
Data Buffer Control Disable
Burst Inhibit (memory bank burst access support)
Extended Hold Time on Read Accesses
(clock cycles inserted)
Page-Based Interleaving
Refresh Enable
SDRAM Operation
18
18
2
2
BCTLD
OP
19
19
3
3
(OR3) 0x1011C
(OR2) 0x10114
Description
Description
20
20
4
4
Table 6-12. Memory Controller Registers (Continued)
ACTTORW
21
21
—
5
5
ORx—UPM Mode Bit Descriptions
SDAM
PSDMR Bit Descriptions
22
22
6
6
(OR5) 0x1012C
(OR4) 0x10124
BL
23
23
BI
7
7
AM
0 = Corresponding bits masked
0 = BCTLx asserted.
0 = Supports
00 = 0
0 = Bank-based interleaving
0 = Refresh services not required.
000 = Normal
001 = CBR refresh
010 = Self refresh
011 = Mode register write
LDOTOPRE
24
24
8
8
Reset: 0
Reset: 0
BSMA
25
25
9
9
(OR7) 0x1013C
(OR6) 0x10134
01 = 1
10
26
10
26
—
WRC
11
27
11
27
Settings
Settings
1 = Corresponding address bits used
1 = BCTLx not asserted
1 = Does not support
10 = 4
1 = Page-based interleaving
1 = Refresh services required
100 = Precharge bank
101 = Precharge all banks
110 = Activate bank
111 = R/W
EAMUX BUFCMD
SDA10
12
28
12
28
Type: R/W
Type: R/W
(OR11) 0x1015C
(OR10) 0x10154
13
29
13
29
EHTR
11 = 8
14
30
14
30
RFRC
CL
0x1090
15
31
15
31
—