MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 86

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

SICR/SICR_EXT
SIPRR/SIPRR_EXT
16–27
3–11,
Reset
Reset
Bits
Bits
2–7
0–2
14
15
Bit
Bit
Bit
HP
GSIU
SPS
XS1P–XSIU1
XS2P–XS8P
16
0
0
0
1
Name
Name
—
XS1P
XS5P
17
1
1
0
0
SIU Interrupt Configuration Register
Highest Priority
Group SIU (relative XSIU priority scheme)
Spread Priority Scheme (relative YCC priority scheme)
SIU Interrupt Priority Register
Priority order
Same as XS1P, but for XSIU2–XSIU8.
18
2
2
0
0
19
3
3
0
1
XS2P
XS6P
Description
Description
20
4
4
0
0
HP
21
5
5
1
1
SIPRR/SIPRR_EXT Bit Descriptions
Table 6-10. Interrupt Registers
SICR/SICR_EXT Bit Descriptions
22
6
6
0
1
XS3P
XS7P
23
7
7
1
1
To retain original priority, program HP to the XSIU1 interrupt number.
0 = Grouped
0 = Grouped
000 = TMCNT asserts its request in the XSIU1 position
001 = PIT asserts its request in the XSIU1 position
010 = Reserved
011 = IRQ1 asserts its request in the XSIU1 position
100 = IRQ2 asserts its request in the XSIU1 position
101 = IRQ3 asserts its request in the XSIU1 position
110 = IRQ4 asserts its request in the XSIU1 position
111 = IRQ5 asserts its request in the XSIU1 position
24
8
8
0
0
Reset:
0
25
9
9
0
1
XS4P
XS8P
10
10
26
1
1
—
11
11
27
1
1
Type: R/W
Type: R/W
Settings
Settings
1 = Spread
1 = Spread
12
12
28
0
0
13
13
29
0
0
(SIPRR_EXT) 0x10C50
(SICR_EXT) 0x10C40
—
—
GSIU
(SIPRR) 0x10C10
(SICR) 0x10C00
14
14
30
0
0
SPS
15
15
31
0
0