MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 19

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

EXT_DBG3
NMI_OUT
DREQ4
DACK3
DACK4
Name
IRQ5
IRQ6
IRQ7
DP5
DP6
DP7
TEA
NMI
TA
Input/Output
Input/Output
Input/Output
Input/Output Transfer Acknowledge
Input/Output Transfer Error Acknowledge
Direction
Output
Output
Output
Output
Input
Input
Input
Input
Input
Data
Table 3-1. External Signals–SIU and Extended Core (Continued)
Interrupt Request 5
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
60x Data Parity 5
The 60x agent that drives the data bus also drives the data parity signals. The value
driven on the data parity five pin should give odd parity (odd number of ones) on the
group of signals that includes data parity 5 and D[40–47].
DMA Request 4
An external peripheral uses this pin to request DMA service.
External Data Bus Grant 3
The MSC8101 asserts this pin to grant PowerPC 60x data bus ownership to an external
PowerPC bus master.
Interrupt Request 6
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
60x Data Parity 6
The 60x agent that drives the data bus also drives the data parity signals. The value
driven on the data parity six pin should give odd parity (odd number of ones) on the
group of signals that includes data parity 6 and D[48–55].
DMA Acknowledge 3
The DMA drives this output to acknowledge the DMA transaction on the PowerPC 60x
bus.
Interrupt Request 7
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
60x Data Parity 7
The 60x master or slave that drives the data bus also drives the data parity signals. The
value driven on the data parity seven pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 7 and D[56–63].
DMA Acknowledge 4
The DMA drives this output to acknowledge the DMA transaction on the PowerPC 60x
bus.
Indicates that a 60x data beat is valid on the data bus. For 60x single beat transfers,
assertion of TA indicates the termination of the transfer. For 60x burst transfers, TA is
asserted four times to indicate the transfer of four data beats with the last assertion
indicating the termination of the burst transfer.
Indicates a bus error. 60x masters within the MSC8101 monitor the state of this pin. The
MSC8101 internal PowerPC bus monitor can assert this pin if it identifies a PowerPC
60x bus transfer that is hung.
Non-Maskable Interrupt
When an external device asserts this line, the MSC8101 NMI input is asserted.
Non-Maskable Interrupt
Driven from the MSC8101 internal interrupt controller. Assertion of this output indicates
that a non-maskable interrupt, pending in the MSC8101 internal interrupt controller, is
waiting to be handled by an external host.
MSC8101 Programmer’s Quick Reference
Description
External Signals
11