MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 73

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MSC8101PG

Manufacturer Part Number
MSC8101PG
Description
MSC8101PG 16-Bit Digital Signal Processor Quick Reference
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
FACR
FDBA
FCBA
12–13 FRM
14–15 FSCL
Bits
10
12
13
14
15
8
9
Bit
Bit
Bit
FOM
FUPD
FADP
FLT
FEN
FSCO
FISL
0
0
0
Name
EFCOP ALU Control Register
EFCOP Data Base Address
EFCOP Coefficient Base Address
1
1
1
Filter Operation Mode
Filter Update
Filter Adaptive Mode
Filter Type
Filter Enable
Filter Shared Coefficients Mode
Filter Input Scale
Filter Rounding Mode
Filter Scaling
2
2
2
3
3
3
Description
4
4
4
Table 6-6. EFCOP Registers (Continued)
5
5
5
FACR Bit Descriptions
6
6
6
7
7
7
00 = Mode 0: Real FIR filter
01 = Mode 1: Full complex FIR filter
10 = Mode 2: Complex FIR filter with alternate real and imaginary outputs
11 = Mode 3: Magnitude
0 = Update mode disabled
0 = Disabled
0 = FIR filter
0 = EFCOP disabled (individual reset) 1 = EFCOP enabled
0 = Coefficients stored sequentially for each channel
1 = Same coefficients used for each channel
0 = Scale both IIR feedback terms and IIR input
1 = Scale IIR feedback terms only
00 = Convergent rounding
01 = Two’s complement rounding
10 = Truncation (no rounding)
11 = Reserved
00 = Scaling factor = 1 (no shift)
01 = Scaling factor = 8 (3-bit arithmetic left shift)
10 = Scaling factor = 16 (43-bit arithmetic left shift)
11 = Reserved
FSCO
8
8
8
Reset: 0
Reset: 0
Reset: 0
FDBA
FDBA
FISL
9
9
9
10
10
10
11
11
11
Settings
1 = Update mode enabled
1 = Enabled
1 = IIR filter
12
12
12
Type: R/W
Type: R/W
Type: R/W
FRM
13
13
13
14
14
14
FSCL
0x0CE0
0x0CC0
0x0CA0
15
15
15

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