MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 20

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

External Signals
12
BADDR[27–28]
PSDDQM[0–7]
PWE[0–7]
PBS[0–7]
INT_OUT
PSDVAL
PSDA10
CS[0–7]
PGPL0
BCTL1
BCTL0
Name
IRQ7
ALE
Input/Output 60x Data Valid
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Data
Table 3-1. External Signals–SIU and Extended Core (Continued)
Indicates that a data beat is valid on the data bus. The difference between the TA pin
and PSDVAL is that the TA pin is asserted to indicate 60x data transfer terminations
while the PSDVAL signal is asserted with each data beat movement. Thus, when TA is
asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not necessarily
asserted. For example when the SDMA initiates a double word (2x64 bits) transfer to a
memory device that has a 32-bit port size, PSDVAL is asserted three times without TA,
and finally both pins are asserted to terminate the transfer.
Interrupt Request 7
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Interrupt Output
Driven from the MSC8101 internal interrupt controller. Assertion of this output indicates
that an unmasked interrupt is pending in the MSC8101 internal interrupt controller.
Chip Select
Enable specific memory devices or peripherals connected to MSC8101 buses.
Buffer Control 1
Controls buffers on the PowerPC 60x data bus. Usually used with BCTL0. The exact
function of this pin is defined by the value of SIUMCR[BCTLC]. See Table 6-8, SIU
Registers, on page -68, for SIUMCR[BCTLC] values.
Burst Address 27–28
Two of five outputs of the 60x memory controller. These pins are used in external master
configuration. They connect directly to memory devices controlled by the MSC8101
memory controller.
Address Latch Enable
Controls the external address latch used in external master 60x bus configuration.
Buffer Control 0
Controls buffers on the PowerPC 60x data bus. The exact function of this pin is defined
by the value of SIUMCR[BCTLC]. See Table 6-8, SIU Registers, on page -68, for
SIUMCR[BCTLC] values.
60x Bus Write Enable
Outputs of the PowerPC 60x bus general-purpose chip-select machine (GPCM). These
pins select byte lanes for write operations.
60x Bus SDRAM DQM
Outputs of the SDRAM control machine. These pins select specific byte lanes of
SDRAM devices.
60x Bus UPM Byte Select
Outputs of the user-programmable memory (UPM) in the memory controller. These pins
select specific byte lanes during memory operations. The timing of these pins is
programmed in the UPM. The actual driven value depends on the address and size of
the transaction and the port size of the accessed device.
60x Bus SDRAM A10
Output from the 60x bus SDRAM controller. This pin is part of the address when a row
address is driven. It is part of the command when a column address is driven.
60x Bus UPM General-Purpose Line 0
One of six general-purpose output lines of the UPM. The values and timing of this pin is
programmed in the UPM.
MSC8101 Programmer’s Quick Reference
Description