MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 77

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

PPC_ACR
16–18 NPQM
Bits
1–3
11
12
13
14
21
27
8
2
3
Bit
APD
PLDP
EAV
ETM
LETM
EPAR
EXDD
ISPS
DBGD
EARB
Name
0
PowerPC 60x Bus Arbiter Configuration Register
—
Address Phase Delay
Pipeline Maximum Depth
Enable Address Visibility
Compatibility Mode Enable
Local Bus Compatibility Mode Enable
Even Parity
Non-MSC8101 Master Connected to Arbitration Lines 0 = Bus master is an MSC8101
External Master Delay Disable
Internal Space Port Size
Data Bus Grant Delay
External Arbitration
1
Description
DBGD
2
Table 6-8. SIU Registers (Continued)
PPC_ACR Bit Descriptions
EARB
3
Reset: Depends on reset configuration sequence
Specifies the number of address tenure wait states for address operations
initiated by 60x bus master.
0 = One
0 = Bank select signals driven on 60x bus address lines (no full address
1 = Bank select signals not driven on address bus (during READ and
0 = Strict 60x bus mode (extended transfer mode disabled)
1 = Extended transfer mode enabled
0 = Extended transfer mode disabled
1 = Extended transfer mode enabled
0 = Odd parity
0 = Memory controller inserts one wait state between the assertion of TS
1 = Memory controller asserts CS on the cycle following the assertion of
0 = MSC8101 acts as 64-bit slave.
1 = MSC8101 acts as 32-bit slave.
0 = DBG asserted with TS if the data bus is free.
1 = DBG asserted one cycle after TS if the data bus is not busy.
0 = Internal arbitration performed. 1 = External arbitration assumed.
visibility).
WRITE commands to SDRAM devices, full address is driven on 60x
bus address lines).
and of CS when the external master accesses an address space
controlled by the memory controller.
TS by an external master accessing an address space controlled by
the memory controller.
4
5
Settings
PRKM
1 = Zero
1 = Even parity
1 = Bus master is not an MSC8101
6
Type: R/W
7
0x10028