MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 132
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MSC8101PG
Manufacturer Part Number
MSC8101PG
Description
MSC8101PG 16-Bit Digital Signal Processor Quick Reference
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.MSC8101PG.pdf
(162 pages)
- Current page: 132 of 162
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EOR
EOR.W
EXTRACT
EXTRACTU
IADD
Mnemomic
Bitwise Exclusive OR on a 16-bit operand
#u16
#u16
Bitwise Exclusive OR on a 16-bit operand in memory
#u16
#u16
#u16
#u16
Extract signed bit field
Db[(offset + width – 1):offset]
Db[offset + width – 1]
width = #U6; offset = #u6
width = Da[13:8]; offset = Da[5:0]
Extract unsigned bit field
Db[(offset + width – 1):offset]
width = #U6; offset = #u6
width = Da[13:8]; offset = Da[5:0]
Add integers (not affected by saturation)
Da + Dn
0
(sign-extension)
Dn[39:width]
DR.L
DR.H
(R)
(SP – u5)
(SP + s16)
(a16)
Dn
(R)
DR.L
(a16)
DR.H
Operation
SP – u5)
(SP + s16)
Dn[39:width]
Table 9-5. Instructions Grouped Alphabetically (Continued)
Dn[(width – 1):0]
Dn[(width – 1):0]
Description
EOR #u16,DR.L {0
EOR #u16,DR.H {0
EOR.W #u16,(Rn) {0
EOR.W #u16,(SP–u5) {0
EOR.W #u16,(SP+s16) {0
EOR.W #u16,(a16) {0
EXTRACT #U6,#u6,Db,Dn
EXTRACT Da,Db,Dn {0
EXTRACTU #U6,#u6,Db,Dn {0
EXTRACTU Da,Db,Dn {0
IADD Da,Dn
{0
{–2
{0
{0
{0
{0
{0
15
U6
Da [5:0]
u6
Da [5:0]
u5 < 64, W}
a16 < 2
s16 < 2
40} {#U6+#u6
40} {0
Assembler Syntax
16
, W}
40} {Da [13:8] +Da[5:0]
40} {Da [13:8] +Da[5:0]
15
, W}
u6
u16 < 2
u16 < 2
u16 < 2
40} {#U6+#u6
u16 < 2
Da [13:8]
40}
u16 < 2
Da [13:8]
16
u16 < 2
16
}
}
16
16
}
U6
}
16
16
}
40}
}
40}
40}
40}
40}
40}
Words
2
2
2
2
3
3
2
2
2
2
1
Cycles
2
2
2
3
3
2
1
1
1
1
1
Type
3
3
3
3
3
3
4
4
4
4
2
Functional
Arithmetic
Bit-Mask
Bit-Mask
Logical
Logical
Group
DALU
DALU
DALU
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