MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 39

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

4
4.1
4.2
Power-on reset
(PORESET)
Hard reset (HRESET)
Soft reset (SRESET)
Software watchdog reset
Bus monitor reset
JTAG reset
Reset
Power-on reset
External hard reset
Software watchdog
Bus monitor
JTAG reset
External soft reset
Reset Causes
Reset Actions for Each Reset Source
Name
Reset Source
Direction
Input
I/O
I/O
PLL and DLL States
Reset Logic
PORESET initiates the power-on reset flow that resets all the MSC8101s and configures various
attributes of the MSC8101, including its clock mode.
The MSC8101 can detect an external assertion of HRESET only if it occurs while the MSC8101 is not
asserting reset. During HRESET, SRESET is asserted. HRESET is an open-drain pin.
The MSC8101 can detect an external assertion of SRESET only if it occurs while the MSC8101 is not
asserting reset. SRESET is an open-drain pin.
When the MSC8101 watchdog count reaches zero, a software watchdog reset is signalled. The enabled
software watchdog event then generates an internal hard reset sequence.
When the MSC8101 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled
bus monitor event then generates an internal hard reset sequence.
When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated.
Yes
No
Table 4-2. Reset Actions for Each Reset Source
Table 4-1. Reset Causes
System Configuration
Sampled
Yes
Yes
Description
HRESET
Driven
Yes
Yes
Other Internal
Logic Reset
Yes
Yes
SRESET
Driven
Yes
Yes
Reset
Core
Yes
Yes