MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 17

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

EXT_BR2
D[61–63]
HRRQ
HACK
HDDS
H8BIT
Name
HDSP
HCS2
DP0
D56
D57
D58
D59
D60
NC
NC
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output 60x Data Bus Bits 61–63
Input/Output
Direction
Output
Input
Input
Input
Input
Input
Input
Data
Table 3-1. External Signals–SIU and Extended Core (Continued)
60x Data Bus Bit 56
In write transactions the 60x bus master drives the valid data on this pin. In read
transactions the 60x slave drives the valid data on this pin.
Receive Host Request
When the HDI16 is programmed to interface with a double host request host bus, this
pin is the receive host request output (HRRQ). The polarity of the host request is
programmable. The host request is an open-drain output.
Host Acknowledge
When the HDI16 is programmed to interface with a single host request host bus, this pin
is the host acknowledge input (HACK). The polarity of the host acknowledge is
programmable.
60x Data Bus Bit 57
In write transactions the 60x bus master drives the valid data on this pin. In read
transactions the 60x slave drives the valid data on this pin.
Host Data Strobe Polarity
When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP).
60x Data Bus Bit 58
In write transactions the 60x bus master drives the valid data on this pin. In read
transactions the 60x slave drives the valid data on this pin.
Host Dual Data Strobe
When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS).
60x Data Bus Bit 59
In write transactions the 60x bus master drives the valid data on this pin. In read
transactions the 60x slave drives the valid data on this pin.
H8BIT
When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or
16-bit mode.
60x Data Bus Bit 60
In write transactions the 60x bus master drives the valid data on this pin. In read
transactions the 60x slave drives the valid data on this pin.
Host Chip Select 2
When the HDI16 interface is enabled, this is the chip-select pin. The polarity of this pin is
programmable.
Used only in PowerPC-only mode. In write transactions the 60x bus master drives the
valid data on this bus. In read transactions the 60x slave drives the valid data on this
bus.
The dedicated signal is a no connect (NC).
The primary (general-purpose) signal is a no connect (NC).
60x Data Parity 0
The 60x agent that drives the data bus also drives the data parity signals. The value
driven on the data parity zero pin should give odd parity (odd number of ones) on the
group of signals that includes data parity 0 and D[0–7].
External PowerPC Bus Request 2
An external master asserts this pin to request PowerPC 60x bus ownership from the
internal arbiter.
MSC8101 Programmer’s Quick Reference
Description
External Signals
9