MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 68

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

HSR
Bits
Bits
0–3
5–7
6–7
0–3
10
11
12
13
14
15
12
13
14
15
4
5
9
Bit
HF[4–7]
HICR
HDM[0–2]
RREQ (HICR = 1) RREQ Status
HM (HICR = 1)
DBTE
DBRE
HCIE
HTFIE
HTEIE
HRFIE
HREIE
HF[0–3]
HTFNF
HTFE
HRFF
HRFNE
HF0
0
Name
Name
Host Status Register
HF1
1
Host Flags
ICR/HCR priority for DMA/Last Address Mode
Host DMA/Last Address Mode Control
ICR[HM] Status
DMA Transmit Burst Enable
DMA Receive Burst Enable
Host Command Interrupt Enable
Host Transmit Not Full Interrupt Enable
Host Transmit Empty Interrupt Enable
Host Receive Full Interrupt Enable
Host Receive Not Empty Interrupt Enable
Host Flags
Host Transmit FIFO Not Full
Host Transmit FIFO Empty
Host Receive FIFO Full
Host Receive FIFO Not Empty
HF2
2
HF3
3
Description
Description
4
Table 6-5. HDI16 Registers (Continued)
5
Reset: Depends on reset configuration sequence
HCR Bit Descriptions
HSR Bit Descriptions
6
7
—
Values reflected in the ISR
See information on host DMA mode control values in the MSC8101
Reference Manual.
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
Values reflect ICR(HF[0–3])
0 = Not empty
0 = Not full
0 = DMA/last address mode defined in HCR; 1 = Defined in ICR
0 = Disabled
0 = Disabled
0 = Full
0 = Empty
8
9
10
11
Settings
Settings
1 = Not full
1 = Empty
1 = Full
1 = Not empty
Type: R
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
HTFNF
1 = Enabled
12
HTFE
13
HRFF
14
HRFNE
0x0040
15