MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 40

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

4.3
4.4
Bit
Bit
EARB
RSTCONF
EE0
HPE/EE1
BTM[0-1]/
EE[4-5]
16
—
Hard Reset Configuration Word
External Configuration Signals
0
Pin
EXMC
BBD
17
1
Reset Configuration
Input line sampled by the MSC8101 at the rising edge of
PORESET.
EONCE Event Bit 0
Input line sampled after core PLL locks. Holding EE[0] at logic 1 at
the exit from reset puts the SC140 core into Debug mode.
Host Port Enable
Input line sampled at the rising edge of PORESET. If asserted, the
Host port is enabled, the PowerPC 60x data bus is 32-bit wide, and
the Host must program the reset configuration word.
Boot Mode
Input lines sampled at the rising edge of PORESET, which
determine the MSC8101 Boot mode.
IRQ7
INT
18
2
MMR
EBM
19
3
20
4
Description
BPS
—
Table 4-4. Hard Reset Configuration Word
Table 4-3. External Configuration Signals
21
5
SCDIS
22
6
TCPC
ISPS
23
7
24
8
BC1PC
IRPC
0
1
0
1
0
1
00 MSC8101 boots from external memory.
01 MSC8101 boots from HDI16.
10 Reserved.
11 Reserved.
25
Reset Configuration Master.
Reset Configuration Slave.
SC140 core starts the normal processing mode after
reset.
SC140 core enters Debug mode immediately after
reset.
Host port disabled (hardware reset configuration
enabled).
Host port enabled.
9
Reset: 0
10
26
—
DPPC
DLLDIS
11
27
Type: R/W
Settings
OUT
NMI
12
28
MODCK_H
13
29
ISB
14
30
15
31
—