MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 63

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MSC8101PG

Manufacturer Part Number
MSC8101PG
Description
MSC8101PG 16-Bit Digital Signal Processor Quick Reference
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
MCTL
SR
Reset
Reset
Bit
Bit
Bit
Bit
Linear addressing
Reverse-carry addressing
M0 used—Modulo addressing
M1 used—Modulo addressing
M2 used—Modulo addressing
M3 used—Modulo addressing
M0 used—Multiple wrap-around modulo addressing
M1 used—Multiple wrap-around modulo addressing
M2 used—Multiple wrap-around modulo addressing
M3 used—Multiple wrap-around modulo addressing
Notes:
SLF
31
15
31
15
0
0
Modifier Control Register
1. All other AM field combinations are reserved and should not be used.
Status Register
LF3
30
R7 AM[3–0]
14
R3 AM[3–0]
30
14
0
0
LF2
29
13
29
13
0
0
AM Mode Descriptions
LF1
28
12
28
12
0
0
VF3
LF0
27
11
27
11
0
0
Address Modifier (AM[3–0]) Bit Descriptions
1
VF2
26
R6 AM[3–0]
10
R2 AM[3–0]
26
10
0
0
Table 6-3. Core Registers
VF1
25
25
9
0
9
0
VF0
24
24
8
0
8
0
23
23
I2
7
1
7
0
Reset: 0
AM3
0
0
1
1
1
1
1
1
1
1
22
22
R5 AM[3–0]
R1 AM[3–0]
I1
S
6
1
6
0
S1
21
21
I0
5
1
5
0
AM2
0
0
0
0
0
0
1
1
1
1
OVE
S0
20
20
4
0
4
0
RM
19
19
DI
3
0
3
0
Type: R/W
Type: R/W
AM1
0
0
0
0
1
1
0
0
1
1
EXP
SM
18
18
R4 AM[3–0]
R0 AM[3–0]
2
1
2
0
17
17
T
1
0
1
0
AM0
0
1
0
1
0
1
0
1
0
1
0x10C92
16
16
C
0
0
0
0

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