SAM3U2E Atmel Corporation, SAM3U2E Datasheet - Page 945
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SAM3U2E
Manufacturer Part Number
SAM3U2E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2E
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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38.7.38
Name:
Address:
Access:
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in
page
Only the first 16 bits (channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
936.
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
31
23
15
–
7
(
------------------------------------------ -
(
----------------------------------------------------- -
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
(
------------------------------- -
(
------------------------------------------ -
2
2
X
CRPD
×
×
×
PWM Channel Period Register
MCK
X
CPRD
CPRD
MCK
MCK
×
PWM_CPRDx [x=0..3]
0x4008C20C [0], 0x4008C22C [1], 0x4008C24C [2], 0x4008C26C [3]
Read-write
MCK
×
CPRD
DIVA
)
×
DIVA
)
30
22
14
)
–
6
or
)
or
(
------------------------------------------ -
CRPD
(
----------------------------------------------------- -
2
×
MCK
CPRD
×
DIVB
MCK
29
21
13
–
5
×
)
DIVB
)
28
20
12
–
4
CPRD
CPRD
CPRD
27
19
11
–
3
“PWM Write Protect Status Register” on
26
18
10
–
2
SAM3U Series
SAM3U Series
25
17
–
9
1
24
16
–
8
0
945
945
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