SAM3U2E Atmel Corporation, SAM3U2E Datasheet - Page 1177

• Manufacturer Part Number: SAM3U2E
• Manufacturer: Atmel Corporation

Specifications of SAM3U2E

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 57
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 5
• Twi (i2c): 2
• Uart: 5
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24 Bus Matrix (MATRIX) ............................................................................ 341
25 Static Memory Controller (SMC) ......................................................... 355
26 Peripheral DMA Controller (PDC) ....................................................... 443
27 Clock Generator ................................................................................... 455
6430E–ATARM–29-Aug-11
23.4 SAM-BA Monitor ................................................................................................336
23.5 Hardware and Software Constraints ..................................................................340
24.1 Description .........................................................................................................341
24.2 Memory Mapping ...............................................................................................341
24.3 Special Bus Granting Techniques .....................................................................341
24.4 Arbitration ..........................................................................................................342
24.5 Write Protect Registers ......................................................................................344
24.6 Bus Matrix (MATRIX) User Interface .................................................................345
25.1 Description .........................................................................................................355
25.2 Embedded Characteristics ................................................................................355
25.3 Block Diagram ...................................................................................................356
25.4 I/O Lines Description .........................................................................................357
25.5 Multiplexed Signals ............................................................................................357
25.6 Application Example ..........................................................................................358
25.7 Product Dependencies ......................................................................................358
25.8 External Memory Mapping .................................................................................359
25.9 Connection to External Devices ........................................................................360
25.10 Standard Read and Write Protocols ................................................................362
25.11 Scrambling/Unscrambling Function .................................................................368
25.12 Automatic Wait States .....................................................................................369
25.13 Data Float Wait States .....................................................................................372
25.14 External Wait ...................................................................................................377
25.15 Slow Clock Mode .............................................................................................383
25.16 NAND Flash Controller Operations .................................................................386
25.17 SMC Error Correcting Code Functional Description ........................................398
25.18 Static Memory Controller (SMC) User Interface ..............................................402
26.1 Description .........................................................................................................443
26.2 Block Diagram ...................................................................................................444
26.3 Functional Description .......................................................................................444
26.4 Peripheral DMA Controller (PDC) User Interface ..............................................447
27.1 Description .........................................................................................................455
SAM3U Series
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