ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 44

• Manufacturer Part Number: ATmega32U4
• Manufacturer: Atmel Corporation

Specifications of ATmega32U4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 14
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 26
• Ext Interrupts: 13
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7.1
7.2
7.3
7.4
7766F–AVR–11/10
Idle Mode
ADC Noise Reduction Mode
Power-down Mode
Power-save Mode
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire
Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This
sleep mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire
Serial Interface address match and the Watchdog to continue operating (if enabled). This sleep
mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run
(including clkUSB).
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, an SPM/EEPROM
ready interrupt, an external level interrupt on INT6, an external interrupt on INT3:0 or a pin
change interrupt can wake up the MCU from ADC Noise Reduction mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-
wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset,
a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface address match, an external level
interrupt on INT6, an external interrupt on INT3:0, a pin change interrupt or an asynchronous
USB interrupt sources (VBUSTI, WAKEUPI), can wake up the MCU. This sleep mode basically
halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. For compatibility reasons with AT90USB64/128 this mode is still present but since
Timer 2 Asynchronous operation is not present here, this mode is identical to Power-down.
CPU
and clk
“Clock Sources” on page
FLASH
, while allowing the other clocks to run.
“External Interrupts” on page 85
ATmega16/32U4
28.
44