ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 286
ATmega32U4
Manufacturer Part Number
ATmega32U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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ATmega16/32U4
• 5 - RWAL - Read/Write Allowed Flag
Set by hardware to signal:
- for an IN endpoint: the current bank is not full i.e. the firmware can push data into the FIFO,
- for an OUT endpoint: the current bank is not empty, i.e. the firmware can read data from the
FIFO.
The bit is never set if STALLRQ is set, or in case of error.
Cleared by hardware otherwise.
This bit shall not be used for the control endpoint.
• 4 - NAKOUTI - NAK OUT Received Interrupt Flag
Set by hardware when a NAK handshake has been sent in response of a OUT/PING request
from the host. This triggers an USB interrupt if NAKOUTE is sent.
Shall be cleared by software. Setting by software has no effect.
• 3 - RXSTPI - Received SETUP Interrupt Flag
Set by hardware to signal that the current bank contains a new valid SETUP packet. An inter-
rupt (EPINTx) is triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an IN endpoint.
• 2 - RXOUTI / KILLBK - Received OUT Data Interrupt Flag
Set by hardware to signal that the current bank contains a new packet. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
Kill Bank IN Bit
Set this bit to kill the last written bank.
Cleared by hardware when the bank is killed. Clearing by software has no effect.
See
page 275
for more details on the Abort.
• 1 - STALLEDI - STALLEDI Interrupt Flag
Set by hardware to signal that a STALL handshake has been sent, or that a CRC error has been
detected in a OUT isochronous endpoint.
Shall be cleared by software. Setting by software has no effect.
• 0 - TXINI - Transmitter Ready Interrupt Flag
Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an OUT endpoint.
286
7766F–AVR–11/10
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