ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 275
ATmega32U4
Manufacturer Part Number
ATmega32U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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22.14.1.1
22.15 Isochronous mode
22.15.1
7766F–AVR–11/10
Underflow
Abort
If the endpoint uses 2 banks, the second one can be read by the HOST while the current is
being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already
ready (free) and TXINI is set immediately.
An “abort” stage can be produced by the host in some situations:
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-
form the following operations:
Table 22-1.
An underflow can occur during IN stage if the host attempts to read a bank which is empty. In
this situation, the UNDERFI interrupt is triggered.
An underflow can also occur during OUT stage if the host send a packet while the banks are
already full. Typically, he CPU is not fast enough. The packet is lost.
It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU
should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)
• after “N” write into UEDATX
• as soon as RWAL is cleared by hardware.
• In a control transaction: ZLP data OUT received during a IN stage,
• In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN
• ...
stage on the IN endpoint
Abort flow
NBUSYBK
Abort done
Endpoint
UEIENX.
Endpoint
TXINE
Abort
Clear
reset
=0
Yes
No
Yes
KILLBK=1
KILLBK=1
No
Disable the TXINI interrupt.
Abort is based on the fact
that no banks are busy,
meaning that nothing has to
be sent.
Kill the last written
bank.
Wait for the end of the
procedure.
ATmega16/32U4
275
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