ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 21

• Manufacturer Part Number: ATmega32U4
• Manufacturer: Atmel Corporation

Specifications of ATmega32U4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 14
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 26
• Ext Interrupts: 13
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.3
5.3.1
5.3.2
5.3.3
7766F–AVR–11/10
EEPROM Data Memory
EEPROM Read/Write Access
The EEPROM Address Register – EEARH and EEARL
The EEPROM Data Register – EEDR
The ATmega16U4/ATmega32U4 contains 512Bytes/1K bytes of data EEPROM memory. It is
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis-
ters, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page 25.
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
• Bits 15..12 – Res: Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and will always read as zero.
• Bits 11..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512Bytes/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly between
0 and E2_END. The initial value of EEAR is undefined. A proper value must be written before
the EEPROM may be accessed.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
360,
page
CC
15
–
EEAR7
7
R
R/W
0
X
7
MSB
R/W
0
is likely to rise or fall slowly on power-up/down. This causes the device for some
365, and
14
–
EEAR6
6
R
R/W
0
X
6
R/W
0
page 349
13
–
EEAR5
5
R
R/W
0
X
5
R/W
0
respectively.
12
–
EEAR4
4
R
R/W
0
X
4
R/W
0
11
EEAR11
EEAR3
3
R/W
R/W
X
X
3
0
R/W
for details on how to avoid problems in these
Table
2
R/W
0
10
EEAR10
EEAR2
2
R/W
R/W
X
X
5-3. A self-timing function, however,
1
R/W
0
9
EEAR9
EEAR1
1
R/W
R/W
X
X
ATmega16/32U4
0
LSB
R/W
0
8
EEAR8
EEAR0
0
R/W
R/W
X
X
EEDR
EEARH
EEARL
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