ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 148
ATmega32U4
Manufacturer Part Number
ATmega32U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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15.6.2
7766F–AVR–11/10
Enhanced Compare/PWM mode
When the bit ENHC4 of TCCR4E register is set, the Enhanced Compare/PWM mode is enabled.
This mode allows user to add an accuracy bit to Output Compare Register OCR4A, OCR4B and
OCR4D. Like explained previously, a compare condition appears when one of the three Output
Compare Registers (OCR4A/B/D) matches the value of TCNT4 (10-bits resolution). In basic
PWM Mode, the corresponding enabled output toggles on the Compare Match. The Enhanced
Compare/PWM mode introduces a bit that determines on which internal clock edge the Com-
pare Match condition is actually signalled. That means that the corresponding outputs will toggle
on the standard clock edge (like in Normal mode) if the LSB of OCR4A/B/D is ‘0’, or on the oppo-
site (next) edge if the LSB is ‘1’.
User will notice that between Normal and Enhanced PWM modes, the output frequency will be
identical, while the PWM resolution will be better in second case.
Writing to the Output Compare registers OCR4A/B/D or reading them will be identical in both
modes. In Enhanced mode, user must just consider that the TC4H register can be up to 3-bits
wide (and have the same behavior than during 2-bits operation). That will concern OCR4A,
OCR4B and OCR4D registers accesses only. Indeed, the OCR4C register must not include the
additional accuracy bit, and remains in the resolution that determines the output signal period.
Figure 15-10. How register access works in Enhanced mode
That figure shows that the true OCR4A/B/D value corresponds to the value loaded by the user
shifted on the right in order to transfer the least significant bit directly to the Waveform genera-
tion module.
The maximum available resolution is 11-bits, but any other resolution can be specified. For
example, a 8-bits resolution will allow to obtain the same frequency than a Normal PWM mode
with 7-bits resolution.
Example:
– PLL Postcaler output = 64 MHz, No Prescaler on Timer/Counter4.
– Setting OCR4C = 0x7F determines a full 7-bits theoretical resolution, and so a
Configuration
500kHz output frequency.
OCR4C<9:0>
TCNT4<9:0>
bits
OCR4A/B/D
True
10
(TC4H)
9
Output Compare Module A/B/D
Waveform Generation
8
9
8
7
7
6
6
Pin Toggle
5
5
(OCR4A/B/D)
4
4
Enhanced
Mode
3
3
2
2
1
1
0
0
ATmega16/32U4
ENHC4
User Interface Side
Timer Logic Side
148
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