ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 253

• Manufacturer Part Number: ATmega32U4
• Manufacturer: Atmel Corporation

Specifications of ATmega32U4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 14
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 26
• Ext Interrupts: 13
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21. USB controller
21.1
21.2
7766F–AVR–11/10
Features
Block Diagram
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•
•
•
•
The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-
ble port memory (DPRAM).
The USB controller requires a 48 MHz ±0.25% reference clock (for Full-Speed operation), which
is the output of an internal PLL. The on-chip PLL generates the internal high frequency (48 MHz)
clock for USB interface. The PLL clock input can be configured to use external low-power crystal
oscillator, external source clock or internal RC (see Section “Crystal-less operation”, page 256).
The 48MHz clock is used to generate a 12 MHz Full-speed (or 1.5 MHz Low-Speed) bit clock
from the received USB differential data and to transmit data according to full or low speed USB
device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is
compliant with the jitter specification of the USB bus.
To comply with the USB Electrical specification, USB buffers (D+ or D-) should be powered
within the 3.0 to 3.6V range. As ATmega16U4/ATmega32U4 can be powered up to 5.5V, an
internal regulator provides the USB buffers power supply.
Figure 21-1. USB controller Block Diagram overview
Supports full-speed and low-speed Device role
Complies with USB Specification v2.0
Supports ping-pong mode (dual bank)
832 bytes of DPRAM:
Crystal-less operation for low-speed mode
– 1 endpoint 64 bytes max (default control endpoint)
– 1 endpoints of 256 bytes max, (one or two banks)
– 5 endpoints of 64 bytes max, (one or two banks)
UCAP
VBUS
D-
D+
USB Regulator
Recovery
DPLL
Clock
UVCC
Interface
USB
clk
48MHz
Div-by-2
AVCC
PLL
&
clk
8MHz
USB DPRAM
ATmega16/32U4
XT1
PLL clock
Prescaler
On-Chip
Clock Mux
IntRC
CPU
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