ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 26

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ATmega32U4

Manufacturer Part Number
ATmega32U4
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega32U4

Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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5.4
5.4.1
5.4.2
5.4.3
5.4.4
7766F–AVR–11/10
I/O Memory
General Purpose I/O Registers
General Purpose I/O Register 2 – GPIOR2
General Purpose I/O Register 1 – GPIOR1
General Purpose I/O Register 0 – GPIOR0
The I/O space definition of the ATmega16U4/ATmega32U4 is shown in
page
All ATmega16U4/ATmega32U4 I/Os and peripherals are placed in the I/O space. All I/O loca-
tions may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data
space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16U4/ATmega32U4 is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-
tions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega16U4/ATmega32U4 contains three General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing global vari-
ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
408.
7
MSB
R/W
0
7
MSB
R/W
0
7
MSB
R/W
0
6
R/W
0
6
R/W
0
6
R/W
0
5
R/W
0
5
R/W
0
5
R/W
0
4
R/W
0
4
R/W
0
4
R/W
0
3
0
3
0
3
0
R/W
R/W
R/W
2
R/W
0
2
R/W
0
2
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
ATmega16/32U4
0
LSB
R/W
0
0
LSB
R/W
0
0
LSB
R/W
0
“Register Summary” on
GPIOR2
GPIOR1
GPIOR0
26

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