S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 96

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Initialization
When performing a byte-wide RCR access, users
need to write the command indicating how the data is
to be used, followed by the data. These commands will
assert the internal signals LOAD_LOW_ADDR,
LOAD_HIGH_ADDR or LOAD_WR_DATA. Only one
signal is asserted at any time: once one is asserted,
the others are deasserted.
The final read/write interface to the external nvRAM is
via the Add-On Reset and Control Register (ARCR).
This mechanism is identical to that used for the PCI’s
RCR, except that the Add-On interface is used to
access the nvRAM via the ARCR. The latency is a bit
longer as well, due to the synchronization that must be
performed between the Add-On clock and the PCI
clock.
While on-chip arbitration logic allows simultaneous
accesses to the nvRAM via the PCI’s RCR and Add-
On’s ARCR (by queuing up the commands), there is
no logic to prevent each interface from overwriting
nvRAM contents. If an interface writes to a memory
location that the other interface has already has writ-
ten to, the value at that location will be overwritten.
What follows are the sequence of steps required to
access the nvRAM via the RCR. All the scenarios
assume that the RCR is being controlled via PCI bus
transactions. By replacing RCR with ARCR in the
examples below, the operations are identical for an
Add-On device.
The following sequence is used to perform nvRAM
writes when accessing the RCR/ARCR in a byte-
wide fashion:
AMCC Confidential and Proprietary
1. Verify that busy bit, RCR(31), is not set by read-
2. Write to RCR(31:29) = “100”, the command to
3. Write to RCR(23:16) with the low address byte.
4. Write to RCR(31:29) = “101”, the command to
ing RCR(31). If set, hold off starting the write
sequence (repeat step 1 until this bit clears).
load the low address byte. This will assert the
internal signal LOAD_LOW_ADDR, which is used
to enable the loading of the low-address register
(NVRAM_LOW_ADDR).
Since signal LOAD_LOW_ADDR is asserted, the
d a t a
N V R A M _ L O W _ A D D R .
LOAD_LOW_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_LOW_ADDR.
load the high address byte. This will assert the
internal signal LOAD_HIGH_ADDR, which is
used to enable the loading of the high-address
register (NVRAM_HIGH_ADDR).
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The busy bit will remain set until the nvRAM interface
has completed writing the data byte to the external
nvRAM, and has verified that the write sequence is fin-
ished. The nvRAM “shuts down” during a write and will
not accept any new commands (does not generate an
ACKNOWLEDGE) until it finishes the write operation.
The S5920 will continue to send commands to the
nvRAM until it responds with an ACKNOWLEDGE,
after which it clears the busy bit, indicating that the
write operation is truly complete. If the busy bit were to
be cleared after the nvRAM interface finished the
write, but before the external nvRAM was actually fin-
ished, a scenario exists where a successive write
would be ignored. In this case, the software driver
5. Write to RCR(23:16) with the high address byte.
6. Write to RCR(31:29) = “000”, a dummy command
7. Write to RCR(23:16) the byte to be written. Since
8. Write to RCR(31:29) = “110”, the command to
9. Poll the busy bit until it is no longer set. Once
Since signal LOAD_HIGH_ADDR is asserted, the
d a t a
NVRAM_HIGH_ADDR. Note that as the nvRAM
address is limited to 11 bits, only the 3 lsbs of this
w r i t e d a t a i s a c t u a l l y u s e d . A s l o n g a s
LOAD_HIGH_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_HIGH_ADDR.
t o d e a s s e r t e i t h e r L O A D _ L O W _ A D D R o r
LOAD_HIGH_ADDR (whichever occurred last),
and to assert internal signal LOAD_WR_DATA.
This signal is used to enable the loading of the
write data register. LOAD_WR_DATA will remain
asserted until another command is issued (load
low/high address, begin read/write). As long as
L O A D _ W R _ D ATA i s a s s e r t e d , a w r i t e t o
RCR(23:16) will continue to overwrite the write
data register.
the signal LOAD_WR_DATA is asserted, the data
will be written to the write data register.
start the nvRAM write operation. This will lead to
the deassertion of LOAD_WR_DATA and will set
the busy bit, RCR(31). The nvRAM interface con-
troller will now initiate a write operation with the
external nvRAM.
cleared, it is now safe to perform another write/
read operation to the external nvRAM. The
XFER_FAIL flag (bit 28) can be used to deter-
mine whether the transfer was successful or not.
If XFER_FAIL is asserted, this indicates that a
t ra n s fe r t o th e n v R A M did n ot re c e i v e a n
ACKNOWLEDGE, and the write transfer should
not be considered successful. This flag remains
set until the start of the next read/write operation.
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Revision 1.02 – April 12, 2007
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