S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 146

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Pass-Thru Operation
S5920 Base Address Register Definition
Certain bits in the Base Address Register have spe-
cific functions:
BADR1:4 bits D31:30 are used only by the S5920.
When the host reads the Base Address Registers dur-
ing configuration cycles, they always return the same
value as D29. If D29 is zero, D31:30 return zero, indi-
cating the region is disabled. If D29 is one, D[31:30]
return one. This operation limits each Pass-Thru
region to a maximum size of 512 Mbytes of memory.
For I/O mapped regions, the PCI specification allows
no more than 256 bytes per region. The S5920 allows
larger regions to be requested by the Add-On, but a
AMCC Confidential and Proprietary
D0
D2:1
D3
D31:30
Memory or I/O mapping. If this bit is clear, the
region should be memory mapped. If this bit is
set, the region should be I/O mapped.
Location of a memory region. These bits
request that the region be mapped in a particu-
lar part of memory. These bit definitions are
only used for memory mapped regions.
Prefetchable. For memory mapped regions,
the region can be defined as cacheable. If set,
the region is cacheable. If this bit is clear, the
region is not.
Pass-Thru region bus width. These two bits are
used by the S5920 to define the data bus width
for a Pass-Thru region. Regardless of the pro-
gramming of other bits in the BADR register, if
D31:30 are zeros, the Pass-Thru region is dis-
abled.
D31
D2
0
0
1
1
0
0
1
1
D30
D1
0
1
0
1
0
1
0
1
Location
Anywhere in 32-bit memory
space
Below 1 Mbyte in memory space
(Real Mode address space)
Anywhere in 64-bit memory
space (not valid for the S5920)
Reserved
Add-On Bus Width
Region disabled
8 bits
16 bits
32 bits
PCI BIOS will not allocate the I/O space and will prob-
ably disable the region.
Figure 82. 8-Bit Active Mode PCI Write
Creating a Pass-Thru Region
Section 3.11 describes the values that must be pro-
grammed into the non-volatile boot device to request
various block sizes and characteristics for Pass-Thru
regions. After reset, the S5920 downloads the con-
tents of the boot device locations 54h, 58h, 5Ch, and
60h into “masks” for the corresponding Base Address
Registers. The following are some examples for vari-
ous Pass-Thru region definitions:
During the PCI bus configuration, the host CPU writes
all ones to each Base Address Register, and then
reads the contents of the registers back. The mask
downloaded from the boot device determines which
bits are read back as zeros and which are read back
as ones. The number of zeros read back indicates the
amount of memory or I/O space a particular S5920
Pass-Thru region is requesting.
54h = BFFFF002h
58h = 3xxxxxxxh
5Ch = FFFFFF81h
60h = 00000000h
NV Memory Contents
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTBE[3:0]
DXFR#
DQ[7:0]
PTWAIT#
PTADR#
ADCLK
1
2
PTADDR Byte0
Revision 1.02 – April 12, 2007
Eh
Pass-Thru region 1 is a 4 Kbyte
region, mapped below 1 Mbyte
in memory space with a 16-bit
Add-On data bus. This memory
region is not cacheable.
Pass-Thru region 2 is disabled.
(D31:30 = 00.)
Pass-Thru region 3 is a 32-bit,
128 byte I/O-mapped region.
Pass-Thru region 4 is disabled.
3
Pass-Thru Region Definition
1h
4
Dh
Byte1
Data Book
5
Bh
Byte2
6
DS1596
7h
Byte3
7
Fh
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