S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 110

• Manufacturer Part Number: S5920Q
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5920Q

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5920 – PCI Product: Mailbox Overview
MAILBOX OVERVIEW
The S5920 has two 32-bit mailbox registers. These
mailboxes are useful for passing command and status
information between the Add-On and the PCI bus. The
PCI interface has one incoming mailbox (Add-On to
PCI) and one outgoing mailbox (PCI to Add-On). The
Add-On interface has one incoming mailbox (PCI to
Add-On) and one outgoing mailbox (Add-On to PCI).
The PCI incoming and Add-On outgoing mailboxes
are the same, internally. The Add-On incoming and
PCI outgoing mailboxes are also the same, internally.
The mailbox status may be monitored in two ways.
The PCI and Add-On interfaces each have a mailbox
status register to indicate the empty/full status of data
bytes within the mailboxes. The mailboxes may also
be configured to generate interrupts to the PCI and/or
Add-On interface. The outgoing and the incoming
mailbox on each interface can be configured to gener-
ate interrupts.
Figure 55. Figure 1. PCI to Add-On Mailbox Register
AMCC Confidential and Proprietary
LOAD ENABLE
PCI BUS
PCI CLK
V
PCI CLK
DD
DQ
REGISTER
MAILBOX
DQ
EN
R
S
MAILBOX
FULL
ADCLK
INTERLOCK
DQ
EN
REGISTER
FUNCTIONAL DESCRIPTION
Figure 1 shows a block diagram of the PCI to Add-On
mailbox registers. Add-On incoming mailbox read
accesses pass through an output interlock register.
This prevents a PCI bus write to a PCI outgoing mail-
box from corrupting data being read by the Add-On.
Figure 2 shows a block diagram of the Add-On to PCI
mailbox registers. PCI incoming mailbox reads also
pass through an interlocking mechanism. This pre-
vents an Add-On write to an outgoing mailbox from
corrupting data being read by the PCI bus. The follow-
ing sections describe the mailbox flag functionality and
the mailbox interrupt capabilities.
OUTPUT
Q
D
ADD-ON BUS
ADCLK
Revision 1.02 – April 12, 2007
RD#
SELECT#
ADR -MB
Data Book
DS1596
110